Secure Hardware
Goals
To design digital hardware which is highly resistant to:
(i) reverse engineering and
(ii) attacks by side channels, by malicious hardware or by software.
Issues Involved or Addressed
Redesign of the logic structure of hardware to resist reverse engineering; malicious hardware impact at run-time; design of block cyphers for encryption and decryption; duplication of digital logic in a non-obvious manner; analysis of cryptographic algorithms and standards such as Bluetooth; homomorphic encryption; mathematical proofs of algorithmic complexity.
Partners/Sponsors
Air Force Research Labs (AFRL), Cisco, Department of Energy, Georgia Tech Research Institute (GTRI) and Sandia National Labs.
Methods and Technologies
- Digital Design
- Encryption
- Digital Systems Test
- Lattice Theory
- FPGA Programming
- VLSI Design
- Complexity Theory
- Hardware/Software Codesign
Majors Sought
Computing: Computer Science
Engineering: Computer Engineering, Electrical Engineering
Preferred Interests and Preparation
EE, CmpE – Background/interest in digital design, embedded systems, VLSI design and hardware/software codesign.
CmpE, CS – Background/interest in encryption, complexity theory and algorithms. Computer architecture would be helpful but is not required.
Advisor
Vincent Mooney
Vincent Mooney
mooney@ece.gatech.edu
Day, Time & Location
Full Team Meeting:
5:00-5:50 Wednesday
Klaus 2350
Subteam meetings scheduled after classes begin.