Secure Hardware

2014 ~ Present | Air Force Research Labs (AFRL), Cisco, Department of Energy, Georgia Tech Research Institute (GTRI) and Sandia National Labs.

Goals

To design digital hardware which is highly resistant to:

(i) reverse engineering and

(ii) attacks by side channels, by malicious hardware or by software.

Issues Involved or Addressed

Redesign of the logic structure of hardware to resist reverse engineering; malicious hardware impact at run-time; design of block cyphers for encryption and decryption; duplication of digital logic in a non-obvious manner; analysis of cryptographic algorithms and standards such as Bluetooth; homomorphic encryption; mathematical proofs of algorithmic complexity.

Methods and Technologies

  • Digital Design
  • FPGA Programming
  • Encryption
  • VLSI Design
  • Digital Systems Test
  • Complexity Theory
  • Lattice Theory
  • Hardware/Software Codesign

Academic Majors of Interest

  • Computer Science
  • Computer Engineering
  • Electrical Engineering

Preferred Interests and Preparation

EE, CmpE – Background/interest in digital design, embedded systems, VLSI design and hardware/software codesign.

CmpE, CS – Background/interest in encryption, complexity theory and algorithms. Computer architecture would be helpful but is not required.

Meeting Schedule & Location

Time 
5:00-5:50
Meeting Location 
Klaus 2350
Meeting Day 
Wednesday

Team Advisors

Dr. Vincent Mooney
  • Electrical and Computer Engineering

Partner(s) and Sponsor(s)

Air Force Research Labs (AFRL), Cisco, Department of Energy, Georgia Tech Research Institute (GTRI) and Sandia National Labs.